This invention relates to semiconductor memory devices, and more particularly to an electrically programmable floating gate type MOS memory.
Electrically programmable memory devices of the floating gate type are disclosed in U.S. Pat. No. 4,112,509 issued to Lawrence S. Wall and my U.S. Pat. No. 4,122,544, both assigned to Texas Instruments, or U.S. Pat. No. 3,984,822, issued to Simko et al. These EPROM devices are programmed by electron tunnelling through the gate oxide which occurs when high current is produced in the channel. The programming efficiency can degrade when series resistance in the path of the programming current lowers the voltage drop across the cell being programmed. This effect is avoided in devices made according to the above-mentioned patents by using metal bit lines and making metal-to-silicon contacts to each cell. While performance is excellent in this regard, the cell size is too large for very dense "VLSI" arrays.
A method for making a very high density EPROM array is disclosed in my U.S. Pat. No. 4,151,021, assigned to Texas Instruments. In this device, elongated N+ diffused moat regions are used as the bit lines, with no metal lines and no contacts. While the density is very high, the problem of series resistance of the bit lines is accentuated.
It is the principal object of the invention to provide an improved electrically programmable semiconductor memory cell. Another object is to provide an electrically programmable cell which is of small cell size when formed in a semiconductor integrated circuit and which can be programmed efficiently. A further object is to provide a method for programming dense arrays of electrically programmable memory cells, without reliance upon individual contacts to each cell.